Thermal-Scalable 3D Parallel-Heat-Sinking Integration Methodology: Key SoC Technology for Large-Scale Parallel Computing

Abstract

Present 3D vertical stacking technology is not thermal-scalable and is unable to stack enough layers to maximize chip performance owing to intolerable hotness.This paper proposes a novel thermal-scalable 3D parallel-heat-sinking(PHS) stacking methodology which stacks all layers parallel to the heat-sinking path.All layers are the same strip shape of short dimension parallel to and long dimension vertical to the heat-sinking path.Therefore instead of thermal through-silicon-via(TSV),each regular silicon substrate provides an independent shorter and perfect heat-conduction path for its attached device layer because of silicon's good heat conductance.As a result,the peak substrate temperature of 3D PHS stacking chips does not increase as they stack many more layers.This paper further proposes an analytical model to compute the peak substrate temperature of 3D PHS stacking chips and to show the thermal-scalability of the methodology.Experiments on 3D integration for the future on-chip thousand-core parallel computing draw the conclusion that the 3D PHS methodology is of advantages including thermal scalability,thermal-TSV free,and high yield high yield.