Integrating 3D Floorplanning and Optimization of Thermal Through-Silicon Vias

Abstract

While 3D ICs help improve circuit performance and energy efficiency through the reduction of average wirelength and the increase in communication bandwidth of on-chip wiring, their thermal management remains one of the most challenging obstacles to their commercialization. We present a physical design flow that integrates thermal-driven 3D floorplanning with placement of thermal through-silicon vias (TSVs). We refer to the latter as localized TSV placement. While the floorplanning phase accounts for wirelength and chip area, the thermal-verification phase inserts thermal TSVs to improve the vertical heat flow in the chip stack. Such additional TSVs help reduce the number and magnitudes of hotspots which, in turn, alleviate the negative impact of heat dissipation on chip performance and reliability. The essence of the flow is to analyze the layered thermal map of the chip stack and then insert thermal TSVs iteratively until the maximal on-chip temperature falls below a pre-selected threshold. To do so, one important step is to accurately determine the location and number of thermal TSVs which have the largest impact on reducing hotspot temperatures. The experimental results show the suitability of our algorithm for significantly reducing maximum chip temperature at reasonable density levels for thermal TSVs (up to 100 K reduction at 0.5 % TSV density). The beneficial impact of thermal-TSV insertion strongly increases with the number of stacked chips.