Abstract
We explore the potential benefits of using spacer engineering to improve Bulk FinFET electrical and thermal characteristics. Based on the comparative study of five different spacer configurations, the spacer with encased air-gap and Si3N4 encapsulation layer is regarded as the most promising gate sidewall scheme for the advanced technology node due to the reduced instinct delay and improved SHEs suppression. The further investigation of the encased air-gap spacer with Si3N4 demonstrates that spacer structure parameters have modulation effects on device performance. With the analysis of the normalized RF, analog, digital, thermal and subthreshold regime property parameters, the suitable air-gap percentage window and the determined optimum spacer structure parameters of 14 nm Bulk FinFET are proposed.
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