Abstract
Current very large-scale integrated (VLSI) chip packaging options, with a special emphasis on the various and chip I/O complexity issues are reviewed, quantitatively. The two basic packaging options reviewed are the hermetic chip carrier (HCC) and the pin grid array (PGA). The impact that chip input/output (I/O) has on the size growth of packages as single chip enclosures, as well as that of the chips themselves, is considered. It is shown that the HCC is inherently more area-efficient for almost any high I/O configured VLSI chip, especially if the chip growth that must be anticipated is considered as I/O's of 400 arc entertained. After quantitative considerations of discrete packaging options are exhausted, it is finally recommended that a multicbip VLSI module should be seriously considered as a more efficient packaging concept. This, however, requires some innovation directed toward the development of adequate prepackaged chip testing. This could be facilitated through the incorporation of physically testable I/O ports on the passivated VLSI chip; e.g., flip chip bumps, tape-automated bonding (TAB), or beam lead chip interconnects.
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