The single-layer readout electronics design and development for CEPC scintillator analog hadronic calorimeter prototype

Abstract

With the progress in modern high-energy physics, the Standard Model is constantly being refined. As the last brick of the Standard Model, the Higgs boson was confirmed to be discovered in the Large Hadron Collider (LHC) in 2012. For the further exploration of the Higgs boson, the Circular Electron Positron Collider (CEPC) is proposed. The baseline detector concept of CEPC is guided by the particle flow principle. The Particle Flow Algorithm (PFA) reconstructs a list of low-level particles and associates every detector hit with these particles. The high granularity hadronic calorimeter (HCAL) represents an essential component of PFA-based detectors. This paper mainly presents the single-layer electronics design and development for the scintillator analog hadronic calorimeter prototype (AHCAL). The single-layer readout electronics consists of front-end electronics board (FEB) and data interface (DIF) board. The FEB carries the silicon photomultipliers (SiPM), plastic scintillators, and the SiPM signal readout circuit. A single SiPM coupled with a scintillator constitute the basic detection unit. The size of scintillator used here is 4 cm×4 cm. A sensitive area of 72×72 cm2 can be covered by the design presented here. 324 SiPMs coupled with scintillators are mounted on each FEB. Besides the huge sensitive area, The AHCAL prototype must also meet strict requirements on the integration and robustness of the electronics. This paper develops a complete single-layer readout electronics design that meets the requirements for use in the AHCAL. The results of beam test shows that the peak of the minimum ionizing particle (MIP) is separated from the pedestal evidently and the signal-to-noise ratio (SNR) is better than 20. The volume required for the electronics is less than 4 cm3 per channel. In addition, the FEB is sufficiently robust to avoid damage during intercontinental transportation. The development of the single-layer electronics represents significant progress in the design of a prototype device that meets the requirement for use in the CEPC.