Abstract
To protect the Advanced Encryption Standard (AES) against physical attacks known as fault injection attacks various fault detection schemes have been proposed. In this paper, a comparative study between the most well-known fault detection schemes in terms of fault detection capabilities and implementation cost has been proposed. In the considered study we implement, separately, the hardware, the temporal and the information redundancy for the 32-bit AES. These schemes are implemented on the Virtex-5 Xilinx FPGA board in order to evaluate their efficiency in terms of area, time costs and fault coverage
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
