A hardware FPGA implementation of fault attack countermeasure

Abstract

To secure the Advanced Encryption Standard (AES) implementation against fault injection attacks known as differential fault analysis attacks, different fault detection schemes have been proposed. The AES is used in many embedded systems to provide security. It has become the default choice for security services in numerous applications. In this paper, a parity fault detection scheme has been presented in order to secure AES. This scheme based on parity comparison between the correct parity of the round output and the predicted parity according to the processing steps of the AES round. Moreover, we discuss the strengths and the weaknesses of this scheme against the fault attacks. Experimental synthesis results show that the fault coverage reaches 99.86% for the proposed scheme. The proposed fault detection scheme has been implemented on Xilinx Virtex-5 FPGA. Its fault coverage, area overhead, frequency degradation and throughput have been compared and it is shown that the proposed scheme allows a trade-off between the implementation cost and the security of the AES.