The Reduction of the Dependence of Leakage Current on Gate Bias in Metal-Induced Laterally Crystallized p-Channel Polycrystalline-Silicon Thin-Film Transistors by Electrical Stressing

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The high dependence of the leakage current on the gate bias that is normally observed in metal-induced laterally crystallized polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) can be reduced effectively by electrical stressing. This brief examined the mechanism for the decrease in the high dependence of the leakage current on the gate bias in p-channel poly-Si TFTs by electrical stressing. This effect increased with increasing stress bias that is applied to the gate or drain. The effective decrease in leakage current dependence on the gate bias was attributed to electron trapping in the gate oxide during electrical stressing. It was found that this trapping occurred near the drain junction, and electron detrapping (or trap site regeneration) was also observed after annealing at temperatures above 350degC, resulting in an increase in leakage current. This brief proposes a device structure with a low dependence of the leakage current on the gate bias through light doping at the drain region.