The peripheral bipolar junction transistor and its relation to predictability in device modeling

Abstract

In advanced bipolar junction transistors, the peripheral transistor at the sidewall of the emitter junction may conduct a significant portion of the total collector current. Because the dopant profiles and carrier transport in this peripheral region are poorly defined, the device- and circuit-level performance of the peripheral transistor are not predictive. We investigate an approach for modeling the peripheral collector current (and base current) to be used in an arbitrary circuit model. This approach is shown to be consistent with two-dimensional numerical device simulation. The ratio of peripheral-to-intrinsic collector current at one bias point is extrapolated from that at an earlier bias point and the variation in emitter debiasing across the intrinsic base resistor. The problem of predictability arises when comparing the above approach with experimental data. Although the approach is consistent with numerical device simulation, the results from the numerical simulations are themselves in disagreement with the measured data. The device simulator and circuit model have to be “tuned” by fitting experimental data for a minimum of two devices and two bias conditions (one low and one high) for a given technology. This allows the correct Gummel number and current gain of the peripheral transistor to be determined and, hence, the definition of other model parameters.