The methodology of testability prediction for sequential circuits

Abstract

Increasingly, test generation algorithms are being developed with the continuous creations of incredibly sophisticated computing systems. Of all the developments of testable as well as reliable designs for computing systems, the test generation for sequential circuits is usually viewed as one of the hard nuts to be solved for its complexity and time-consuming issue. Although dozens of algorithms have been proposed to cope with this issue, it still remains much to be desired in solving such problems as to determine 1) which of the existing test generation algorithms could be the most efficient for some particular circuits (by efficiency, we mean the Fault Coverage the algorithm offers, CPU time when executing, the number of test patterns to be applied, etc.) since different algorithms would be preferable for different circuits; 2) which parameters (such as the number of gates, flip-flops and loops, etc., in the circuit) will have the most or least influences on test generation so that the designers of circuits can have a global understanding during the stage of designing for testability.