Abstract

Distributed computing attempts to aggregate different computing resources available in enterprises and in the Internet for computation intensive applications in a transparent and scalable way. Digital test generation aims to find minimal set of test vectors to obtain maximum fault coverage for digital electronic circuits. In this paper we focus on distributed environment and parallelization of the computationally intensive genetic algorithm based test generation for sequential circuits. We discuss the concept and implementation of our system infrastructure, task partitioning, allocation, test generation algorithm and results.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.