The impact of silicon nano-wire technology on the design of single-work-function CMOStransistors and circuits

Abstract

This three-dimensional exploratory study on vertical silicon wire MOS transistors withmetal gates and undoped bodies demonstrates that these transistors dissipate less powerand occupy less layout area while producing comparable transient response with respect tothe state-of-the-art bulk and SOI technologies. The study selects a single metal gate workfunction for both NMOS and PMOS transistors to alleviate fabrication difficultiesand then determines a common device geometry to produce an OFF currentsmaller than 1 pA for each transistor. Once an optimum wire radius and effectivechannel length is determined, DC characteristics including threshold voltage roll-off,drain-induced barrier lowering and sub-threshold slope of each transistor aremeasured. Simple CMOS gates such as an inverter, two- and three-input NAND, NORand XOR gates and a full adder, composed of the optimum NMOS and PMOStransistors, are built to measure transient performance, power dissipation and layoutarea. Simulation results indicate that worst-case transient time and worst-casedelay are 1.63 and 1.46 ps, respectively, for a two-input NAND gate and 7.51 and7.43 ps, respectively, for a full adder for a fan-out of six transistor gates (24 aF).Worst-case power dissipation is 62.1 nW for a two-input NAND gate and 118.1 nWfor a full adder at 1 GHz for the same output capacitance. The layout areas are0.0066 µm2 for the two-inputNAND gate and 0.049 µm2 for the full adder circuits.