Silicon Nanowire Technology for Applications in the Field Programmable Gate Array Architectures

Abstract

This study presents the use of vertical, ultra low-power silicon nanowire transistors in building a Field Programmable Gate Array (FPGA) architecture. The device design section of this study includes work function engineering and optimization of transistor body dimensions to minimize intrinsic energy dissipation and transient response of a single transistor. Once an optimum combination of metal work function, channel length and device radius is determined, an FPGA cluster that consists of three 4-input Look-Up-Tables (4-LUT) is formed; its transient performance, power dissipation and layout area are measured. Post-layout simulation results indicate that the worst-case read and write propagation delays for a 4-LUT are 62 ps and 68 ps, respectively; the worst-case propagation delay of a cluster increases to 72 ps for a fan-out of one and 97 ps for a fan-out of three identical clusters. The worst-case power dissipation is approximately 3.1 μW for a 4-LUT and 10.2 μW for a cluster at 10 GHz. The cluster layout which contains three 4-LUTs occupies approximately 8.0 μm 2 .