The Impact of n-p-n Selector-Based Bipolar RRAM Cross-Point on Array Performance

Abstract

Recently, we have presented a circuit model of the n-p-n selector, validated by experimentally calibrated TCAD data and implemented in SPICE for cross-point memory array performance analysis. In this paper, we study the array circuit performance during memory operations and present five interesting insights. First, power consumption minimization during set/reset operation produces the dominant constraint that defines selector/memory pairing, and consequently the cross-point nonlinearity, i.e., ON-OFF current ratio (KI). Second, an optimal KI exists (e.g., 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> for 1-M array size), which implies that excessively higher KI degrades performance. Third, parallel read operation (i.e., N bits/read) can be performed and N increases with higher resistance in low-resistance state (RLRS) without compromising read margin (RM). Fourth, higher resistance ratio improves RM. Finally, read circuit with an improved sensitivity is highly attractive as 2× lesser RM requirement can improve parallel read capability by 10×.