Designing a differential 3R-2bit RRAM cell for enhancing read margin in cross-point RRAM arrays

Abstract

Conventional memories face serious design challenges as process feature size of transistor shrinks to ultra-low sizes, hence the need for having an alternative for conventional memory technologies is inevitable. The cross-point architectures of resistive random access memories (RRAM) have been introduced as a cost-competitive and high bit-density candidate to replace flash memories. However, deficiencies like sneak leakage current has been a major barrier to reach this goal by reducing the read margin and increasing the power consumption. In order to tackle the mentioned drawbacks in the cross-point architectures, various approaches like differential 2R-1bit and complementary RRAM cells have been proposed, but these solutions have either degraded the density or increased the delay of the read operation. In this paper, in order to make a better trade-off between density, read margin, and power consumption, a 3R-2bit cross-point architecture has been proposed that stores two-bit data in three resistive RRAM elements. In addition, a sense-before-write technique has been applied to maintain endurance and power consumption by preventing excessive write operation. To show advantages of the proposed scheme during the read operation, the simple and the differential 2R-1bit cross-point architectures have been compared with the 3R-2bit architecture of the same bit size under different array sizes. The results show significant improvement in read margin as well as saving up to 90% in static power consumption compared to the differential 2R-1bit scheme.