The impact of interface roughness scattering and degeneracy in relaxed and strained Si n-channel MOSFETs

Abstract

The continual scaling of the conventional MOSFET architecture is reaching its fundamental limit, requiring intolerably thin gate oxides and high channel doping that lead to low device performance and high leakage. Meeting the requirements of the next generation technology nodes requires a departure from the standard MOSFET design both in terms of new materials and architectures. One of the most the promising candidates is strained Si which delivers significant enhancements in device performance with relatively small changes in the overall device design and technology. A major advantage of the strained Si MOSFET architecture is that the overall CMOS performance may be improved due to the enhanced transport of both electrons and holes within the strained layer. In this work we use Monte Carlo simulations to study the performance improvements in nano-scale strained Si MOSFETs. We present useful interpolation formulae for the essential material parameters necessary for accurate device simulation of the strained n-channel Si/SiGe material system. Our Ensemble Monte Carlo simulations indicate that the experimentally observed improvements in surface n-channel strained Si devices are partially related to a smoother strained Si/SiO 2 interface compared to the relaxed Si/SiO 2 interface. The use of degenerate carrier-statistics is crucial in the understanding of carrier transport not only in the high-doped regions which occur in modern scale strained Si-MOSFETs, but also in the strained channel with its reduced density of states.