Abstract
Based on comprehensive calibration to experimental device characteristics, Monte Carlo simulations have been performed to assess the device performance of sub- 100nm Si and strained Si MOSFETs with high-k dielectrics, with and without consideration of soft optical phonon scattering induced by the introduction of high-*: dielectrics. The impact of interface roughness scattering on the performance enhancement of strained Si MOSFETs has also been evaluated.KeywordsGate DielectricInversion LayerInterface RoughnessEquivalent Oxide ThicknessEnsemble Monte CarloThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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