Abstract
The High Luminosity LHC (HL-LHC) will require a significant upgrade of the readout electronics for the CMS Electromagnetic Calorimeter (ECAL). The Very Front-End (VFE) output signal will be sampled at 160 MS/s (i.e. four times the current sampling rate) with a 13 bits resolution. Therefore, a high-speed, high-resolution ADC is required. Moreover, each readout channel will produce 2.08 Gb/s, thus requiring a fast data transmission circuitry. A new readout architecture, based on two 12 bit, 160 MS/s ADCs, lossless data compression algorithms and fast serial links have been developed for the ECAL upgrade. These functions will be integrated in a single ASIC which is currently under design in a commercial CMOS 65 nm technology using radiation damage mitigation techniques.
Highlights
The High Luminosity LHC (HL-LHC) will require a significant upgrade of the readout electronics for the CMS Electromagnetic Calorimeter (ECAL)
These functions will be integrated in a single ASIC which is currently under design in a commercial CMOS 65 nm technology using radiation damage mitigation techniques
The CMS ECAL upgrade foresees a redesign of the front-end electronics in order to cope with the new, more demanding requirements
Summary
The APDs are readout by a MultiGain Pre-Amplifier (MPGA) [2] which provides three outputs with different gain (namely ×1, ×6 and × 12) for each APD. The MPGAs and ADCs are hosted by a Very Front-End (VFE) card connected to the APDs via kapton cables. The FENIX output is sent out via an optical transceiver [5] to the DAQ and trigger systems. The FENIX and the optical transceiver circuitry are mounted on a Front-End (FE) card, which controls five VFE cards. The TIA provides two output gains (namely ×1 and × 10) which are fed to a dual 12-bit, 160 MS/s ADC. The ADC data, after gain selection and data compression, are connected to the lpGBT optical transceiver [7] without data concentrator electronics
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