Abstract
Using Poisson statistics, a model for the survival probability of integrated memory circuits having both hard and soft error bit failure mechanisms is developed. Calculations are made over a range of soft error generation rates and erasure intervals for both single and double error correction. It is shown that even if the soft errors are erased effectively instantaneously, there is still an impact on the probability of system survival which is a function of soft error generation rate, and that in the case of instantaneous erasure of soft errors, a system with N bit error correction will have a probability of survival at least as good as the same system with N-1 bit error correction, no matter how high the soft error generation rate.
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