An Efficient Decoding of SEC-DED-DAEC Code with Odd-Column-Weight H-matrix

Abstract

AbstractThe most familiar way to minimize the influence of soft error in the memories is the employment of suitable error correcting codes (ECCs). The codes like single error correction (SEC) and single error correction-double error detection (SEC-DED) have been enormously employed for the detection and correction of double and single errors, respectively, in the memory systems. Single error correction-double error detection-double adjacent error correction (SEC-DED-DAEC) codes are the simplest form of adjacent ECCs which are proficient of correcting adjacent double errors along with the SEC-DED capability. An assortment of SEC-DED-DAEC codes have already been presented in this regard. But the major limitations of these codes are higher decoding complexities and mis-correction rate. In this paper, an efficient decoding technique has been presented to minimize the area and delay requirement of SEC-DED-DAEC codes with odd-column-weight H-matrix.KeywordsMemorySoft errorsECCsSEC-DED-DAECFPGA