The design and electrical characteristics of high-performance single-poly ion-implanted bipolar transistors

Abstract

A 0.8 mu m high-performance single-poly bipolar transistor with sub-50 ps ECL gate delay is described. The design concepts that distinguish this single-poly transistor from other single-poly transistors are presented, and the process and device parametrics are reviewed. A low-resistance ion-implanted extrinsic base was realized; the sheet resistance was 85 Omega / Square Operator and the junction depth 0.3 mu m. A self-aligned profile scheme was implemented to place the heavily doped extrinsic base region 0.2 mu m away from the emitter. As with the LDD profile in MOSFETs, a link region of medium implant dose was formed to bridge the intrinsic base and the extrinsic base and to buffer the heavily doped emitter and extrinsic base. The silicon surface was not etched throughout the process, and the surface remained planar during the intrinsic base process to facilitate the formation of a very shallow vertical profile. A base width of 105 nm was obtained. Experimental hardware shows that, at 0.8 mu m design rules, the f/sub t/ of transistors reach 16 GHz. With an optimized link, the emitter-base junction breakdown and collector-emitter punchthrough characteristics are no longer affected by the extrinsic base and correlate well with the intrinsic-base implant. As a result, both high-voltage analog and low-voltage high-speed logic devices can be built on the same chip by applying different implant conditions.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>