The board level reliability performance and process challenges of ultra-thin WLP (package height < 250 μm)

Abstract

the trends of wafer level package (WLP) development are to be with small size and low profile feature. In this study, an ultra-thin WLP with overall package height less than 250 μm is presented to demonstrate the board level performance of thin silicon thickness with small bump height. The 4-layer fan-in WLP structure (2 passivation layers, 1 RDL metal layer and 1 UBM layer) with die size 3 × 3 mm2 and ball pitch 300 μm is used for evaluation. The micro-ball with 130 μm ball diameter is used and the silicon wafer is ground to relatively thin, from typical 305 μm to 100 μm to have an overall package height less than 250 μm. The performance of board level thermal fatigue and accelerated drop shock with enhanced bump stack-up are studied and compared for different silicon thickness and ball size. Furthermore, SMT with and without under-fill process for ultra-thin WLP are also collected and discussed. Efforts have also been made to understand the component level package fracture strength and failure modes post three point bending test.The results show comparable board level performance in ultrathin WLP with enhanced bump stack-up. As for the component level bending test, the origin of crack propagation and fracture failure mode are analyzed to understand the fracture strength variation.