Abstract
As design trends move toward nanometer technology, new problems due to noise effects lead to a decrease in reliability and performance of VLSI circuits. Crosstalk is one such noise effect which affects the timing behaviour of circuits. In this paper, an efficient Automatic Test Pattern Generation (ATPG) method based on a modified Fanout Oriented (FAN) to detect crosstalk‐induced delay faults in VLSI circuits is presented. Tests are generated for ISCAS_85 and enhanced scan version of ISCAS_89 benchmark circuits. Experimental results demonstrate that the test program gives better fault coverage, less number of backtracks, and hence reduced test generation time for most of the benchmark circuits when compared to modified Path‐Oriented Decision Making (PODEM) based ATPG. The number of transitions is also reduced thus reducing the power dissipation of the circuit.
Highlights
As a consequence of technological advances which have resulted in an increase of VLSI chip density, increased number of interconnect layers and in an improvement of timing performances, the test for static stuck-at faults only has turned out to be insufficient, and it is required to deal with physical defects which affect the timing behavior of a given circuit
A new modified Fanout Oriented (FAN)-based Automatic Test Pattern Generation (ATPG) algorithm has been proposed that increases the fault coverage with reduced number of transitions and permits safe testing of low power circuits
In test generation for crosstalk delay fault, the number of objectives is to be a satisfied is larger compared to stuck at faults
Summary
As a consequence of technological advances which have resulted in an increase of VLSI chip density, increased number of interconnect layers and in an improvement of timing performances, the test for static stuck-at faults only has turned out to be insufficient, and it is required to deal with physical defects which affect the timing behavior of a given circuit Various noise sources such as crosstalk and power supply noise have a significant impact on the timing performance of Deep Submicron (DSM) designs. The test generator detects crosstalk faults that produce delay affect at the primary output This algorithm reduces the number of transitions when compared to PODEM algorithm and reduces the power dissipation in CMOS circuits.
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