Ternary SRAM for low power applications

Abstract

Design and Performance verification of Ternary CMOS SRAM is presented in this paper. Ternary SRAM is designed in 180nm, 90nm & 65nm technology process. The Ternary SRAM cell consists of two cross coupled Ternary inverters. READ and WRITE operations of the Ternary SRAM cell are performed with the help of Sense Amplifier, Tritline Conditioning circuits and Fast Decoders using TSPICE. The proposed work can be used for Low Power Application as the Fast Decoders use less number of Transistors compared to the conventional Decoders. The Ternary SRAM array module (1X1) in 65 nm technology consumes only 0.608mW power and data access time is about 9.88ns.