Term Trees in Application to an Effective and Efficient ATPG for AND–EXOR and AND–OR Circuits

Lech Jóźwiak,Marek Perkowski,Aleksander Ślusarczyk

doi:10.1080/10655140290009837

Lech Jóźwiak, Marek Perkowski + Show 1 more

Open Access

https://doi.org/10.1080/10655140290009837

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Abstract

A compact data representation, in which the typically required operations are performed rapidly, and effective and efficient algorithms that work on these representations are the essential elements of a successful CAD tool. The objective of this paper is to present a new data representation—term trees (TTs)—and to discuss its application for an effective and efficient structural automatic test‐pattern generation (ATPG). Term trees are decision diagrams similar to BDDs that are particularly suitable for structure representation of AND–OR and AND–EXOR circuits. In the paper, a flexible algorithm for minimum term‐tree construction is discussed and an effective and efficient algorithm for ATPG for AND–EXOR and AND–OR circuits is proposed.The term trees can be used for many other purposes in logic design and in other areas—for all purposes where compact representation and efficient manipulation of term sets is important. The presented experimental results show that term trees are indeed a compact data representation allowing fast manipulations. They form a good base for algorithms considering the function′s and circuit′s term structures.

Highlights

Binary decision diagrams (BDDs) have been recognized as efficient means to model and manipulate Boolean function [1,2], and are used for design, verification and testing of digital circuits [3 – 6]
The results clearly show the flexibility, efficiency and effectiveness of our algorithm: we can trade off the run-time of the algorithm against the solution quality, we can handle large term sets in less than a second and the algorithm constructs the optimal or nearoptimal Term Trees (TTs)
The implemented automatic test-pattern generation (ATPG) program has all required features. It guarantees 100% coverage of all non-redundant single stuck-at faults, because it constructs and keeps the test patterns for all faults from the fault model and it works until all faults are covered

Summary

Introduction

Binary decision diagrams (BDDs) have been recognized as efficient means to model and manipulate Boolean function [1,2], and are used for design, verification and testing of digital circuits [3 – 6] They are applied in functional testability analysis and functional automatic test-pattern generation (ATPG) [2,7 – 9]. A hundred percent fault coverage tends to be more important than a strictly minimal test set, because a lower coverage means that some faults of substantial probability remain untested, while a near-minimal test set only means that the testing time will be a bit longer It is important for a structural test-pattern generator to be efficient. To achieve effective and efficient ATPG, it is very important to have compact data representations in which the typical operations related to ATPG are fast, and to have effective and efficient algorithms that work on these representations

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