Temperature scaling for 35 nm gate length high-performance CMOS

Abstract

It is commonly assumed that reducing the source–drain extension (SDE) junction depth is a key element for next-generation technology nodes. This can either be achieved by reducing the implantation energy or by reducing the thermal budget of the annealing process. In this paper, we will demonstrate that for transistors with an optimum balance between AC and DC performance a reduction in junction depth results only in very little improvement of the short-channel behaviour for spike anneals in the temperature range between 1050 and 1130 °C. On the other hand, reduced temperatures allow a reduction in in-die parameter variation and therefore improved product performance. There exists an optimum temperature which represents a compromise between reduced parameter variation and reduced dopant activation. For improved threshold voltage roll-off we introduced heavily doped low-energy halos, thus obtaining a physical gate length of 35 nm. The problem of increased drain resistance due to reduced activation at lower temperatures and counter-doping with high halo implant doses was solved by optimizing the lateral diffusion of the deep source–drain regions. All electrical data have been extracted from our triple-spacer transistor architecture, manufactured in 90-nm production technology. An outlook will be given for alternative device concepts, such as SPE and Laser anneal and asymmetric devices.