Implantation-dominated junction depths of low-temperature and electron-beam-annealed as source—Drain regions

Abstract

The deep penetration of implanted As is reported and its effect On source-drain regions in NMOS devices is examined. When annealing methods to minimize diffusion are used and the initial implant profiles are not modeled accurately to take into account deep penetration, the junction depths predicted by simulation will be shallower than those obtained in practice. This is verified by comparing experimental results with predicted profiles obtained from two process simulators that use different implantation models. It is shown that a Pearson IV distribution can accurately describe the as-implanted profile of As in Si. From measurements of implanted As profiles annealed Using furnace and electron-beam methods, it is found that junction depths determined by implantation can be unchanged at low backgrounds, even after relatively high-temperature (1000°C) furnace anneals. As a consequence, low-temperature furnace or transient annealing does not yield the expected reduction in junction depth, while resulting in a significant increase in sheet resistivity.