Technology design for high current and ESD robustness in a deep submicron CMOS process

Abstract

The intrinsic ESD/EOS robustness of a technology is determined by the sensitivity to thermal initiated second breakdown. We show, for the first time, high current and ESD robustness results for a deep submicron CMOS technology with drawn poly gate lengths of 0.35 /spl mu/m and oxide thicknesses down to 4.5 nm. It is shown that a transistor design window can be determined for optimized drive current and good robustness, while maintaining low off currents. An important observation is that robustness increases for smaller channel lengths and is directly proportional to the transistor drive current. Hence, robust deep submicron technologies can be designed with optimized transistor performance without using additional masks or increasing process complexity. >