Abstract
Low-voltage (LV), low-power (LP) circuit design requires special attention on device behavior, and the best circuit topology needs to be chosen to meet the design challenges. With the scaling of MOS devices, supply voltage is reduced with each technological leap, but the threshold voltage and the drain-to-source saturation voltage are not scaling at the same rate because of the subthreshold current consideration in mixed-signal environment. Therefore, conventional circuit design topologies are not best suited for deep submicron (DSM) CMOS design. This chapter is a brief overview of the scaling concept of MOS devices and low-power circuit design topologies using deep submicron CMOS process.
Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
