Abstract
The goal of this paper is to investigate design parameters of the CMOS STI diodes, intended to be used as ESD protection devices, and evaluate their performance for use in the deep submicron CMOS process. The 2-D simulations of multiple diode structures and geometries have been performed using SEQUOIA Device Designer, and the results allow to accurately predict the failure point and to optimize the different diode structures for high-speed RF applications. The proposed methodology can be used in practice to aid the design of ESD protection in deep submicron CMOS.
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