Technology computer-aided design simulation study for a strained InGaAs channel n-type metal-oxide-semiconductor field-effect transistor with a high-k dielectric oxide layer and a metal gate electrode

Abstract

The stress distributions in the InGaAs channel regions of strained InGaAs metal-oxide-semiconductor (MOS) field-effect transistors with high-k dielectric layer, metal gate, and InGaAs alloy souce/drain (S/D) stressors were studied with three-dimensional process simulations. It was shown that the geometric effects, such as channel width and length, could impact the achievable transistor performance gains. In this work, high-performance III-V MOS devices were achieved by stressors, such as S/D stressors, with the InGaAs alloy material. The resulting mobility improvement was analyzed by the Monte Carlo simulations. Tensile stress along the transport direction was found to dominate mobility gain while narrower devices (<1 μm), and a decrease of tensile stress along the channel direction contributed to a decrease in mobility gain owing to the decreasing width. This work helps the future III-V-based MOS device design and demonstrates that strain engineering is important for future nanoscale device technology.