TCAD simulation of a double L‐shaped gate tunnel field‐effect transistor with a covered source–channel

Abstract

In this work, the authors propose and simulate a double L-shaped gate tunnel field-effect transistor (DLG-TFET) with the covered source-channel. The proposed structure improves the ON-state current by increasing the linear tunnelling area and has excellent subthreshold characteristics. The simulation focuses on the performance improvement of the device under different longitudinal gate length L g , interlayer silicon thickness T si , gate and source overlap length L ov , and covered source depth L s . For optimal parameters, the ON-state current of the proposed DLG-TFET increases up to 3.53 × 10 -5 A/μm, and the current switch ratio( I on / I off ) is 4.28 × 10 11 at room temperature, moreover, a minimum subthreshold swing (SSmin) and an average subthreshold swing (SSave) are as low as 32.2 and 52.9 mV/Dec, respectively. Meanwhile, this work uses mixed device-circuit simulations to predict the performance of the inverter circuit implemented with proposed DLG-TFET.