Abstract
AbstractThe rapid rise of standby power in nanoscale MOSFETs is slowing classical scaling and threatening to derail continued improvements in MOSFET performance. Strain-enhancement of carrier transport in the MOSFET channel has emerged as a particularly effective approach to enable significant performance improvements at similar off-state leakage. In this paper we describe how strain effects are modeled within the context of TCAD process and device simulation. We also use TCAD simulations to review some of the common approaches to engineer strain in MOSFETs and to explain how strain impacts device and circuit characteristics.
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