3D TCAD Simulation of nanoscale Multi-Gate FETs (MuGFETs)

Abstract

Aggressive scaling of bulk MOS device dimensions has been the major contributor driving improvements in integrated circuit performance. Due to limitations on gate oxide thickness, and source/drain junction depth, further scaling of MOSFET devices in the sub-50 nm process generation will be difficult, if not impossible. New device architecture and new material combinations are therefore needed to overcome technological challenges. Despite the added process complexity, double (FinFET) or triple (Tri-Gate) gate Multi-Gate FET (MuGFET) devices are emerging as strong candidates for low power or high performance applications in the future. This work report on the theoretical design evaluation of MuGFETs using commercial three-dimensional (3D) TCAD simulation tool. Because of three dimensional geometry of MuGFETs and complex channel profiles required to adjust the threshold voltage beyond 50 nm gate length, conventional 1D or 2D TCAD (process and device simulation) simulations are not directly applicable and hence not suited well from the point of view of accuracy and predictability. All critical process steps (i.e., channel implant, gate oxide growth, extension implant, halo implant, spacer formation and source-drain implant) for tri-gate MuGFETs on standard SOI have been included in the process simulation. The total number of mesh points for the half-device was approximately 180,000, while the processing time was 10-12 hours. Device simulations have been performed using drift diffusion model taking into account quantum confinement effects, bandgap narrowing effects, low field (doping and temperature dependence) and high field mobility models including surface scattering model of Lombardi.