Abstract
Systolic/wavefront array based concurrent processing is making a significant impact in signal processing applications and, given the structural similarities, can be expected to play a similar role in information processing for control engineering. In this paper, the problems of direct application of existing architectures to this area (which requires both high speed and short processing delay) are reviewed and two families of architectures are presented for SISO and some MIMO real-time control systems design. These arrays offer a processing delay time of one or two cycles and a high throughput rate near the maximum for word-level pipelining. Pipelining to a deeper level and mapping an array onto the IMS A100 parallel signal processors are also discussed.
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