Abstract

Systolic wavefront array architectures for real-time digital control system design are considered. Described is the development of word-level systolic and and wavefront architectures for recursive filtering and on-line feedback control schemes. Each of these arrays uses only one type of cell and has the same array configuration. These offer a word-level shortest processing delay (or system latency) of one cycle, while retaining a very high throughput rate, and hence are applicable to real-time feedback control engineering problems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

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