Abstract
Systolic/wavefront array based concurrent processing is making a significant impact in signal processing applications and, given the structural simi1arities, can one expected to play a similar role in information processing for control engineering. In this paper, the problems of direct application of existing architectures to this area (which requires both high speed and short processing delay) are reviewed and two families of architectures are presented for SISO and some MIMO real-time control systems design, these arrays offer a processing delay time of one or two cycles and a high throughput rate near the maximum for word-level pipelining. Pipelining to a deeper level and mapping an array onto the IMS A100 parallel signal processors are also discussed
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
