Abstract
This paper presents two classes of systolic architectures, suitable for VLSI implementation, for finite field inversion and division based on a modified Euclidean algorithm. These architectures involve O(m/sup 2/) area-time product and O(m) latency. One architecture class utilizes adder circuits in its centralized control mechanism and its critical path delay depends on the implementation of the adders. The other class implements the control mechanism in distributed fashion, does not use any adders, and achieves a critical path delay of two logic gate delays. These architectures achieve better overall performances when compared with previously proposed architectures.
Published Version
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