Systematic Study of Temperature and VDD Impact to Read Current and Standby Leakage of SRAM in Finfet Technology

Abstract

Static random access memorie (SRAM) are used as cache memory in modern embedded system applications. Read current and standby leakage are used to characterize SRAM speed and power consumption. Read current mainly dominated by N-type transistor device performance, while standby leakage will be an accumulation of all single transistor leakage. SRAM single transistor performance and leakage have strong correlation with V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> and temperature. In this paper, V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> and temperature impact to SRAM read current and standby leakage is systematically studied. When V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> is set from 0.90V to 0.50V, both SRAM read current and standby leakage will become smaller, which can be ascribed to single transistor Idsat and leakage reduce. When temperature change from −40°C to 125 °C, both HD/HC standby leakage increase drastically, while read current show no obvious change. Standby leakage increase is induced by single device leakage trend up.