Performance evaluation of SRAM cells for deep submicron technologies

Abstract

In this paper, different Static RAM (SRAM) cell structures have been analysed in deep submicron regions. A 6T, 7T, 8T and 9T SRAM cell have been compared on the basis of Static Voltage Noise Margin (SVNM), Write Trip Voltage (WTV), Static Current Noise Margin (SINM), Write Trip Current (WTI), Active Leakage Current, Cell Standby Leakage Current, Read Current and Data Retention Voltage (DRV). The recent N-curve method is used over the traditionally used Butterfly Curve method for better analysis in submicron regions. The SRAM cell simulations are performed on 22nm, 32nm and 45nm CMOS technology nodes. The results show that the 6T SRAM cell has the poorest read and write margins and the highest active leakage, standby leakage and read currents across all technology nodes. Also, the 7T cell structure shows the best performance, exhibiting the highest write margins, the lowest active leakage current, lowest data retention voltage and the lowest read and standby-leakage currents across all technology nodes.