Power Optimization Analysis of Different Sram Cells Using Transistor Stacking Technique

Abstract

Nowadays optimization of power is a major challenge in VLSI industry. As the density of the memory systems increases, the power consumption also increases. SRAM cell is most fundamental component for all the memory devices like cache memories and CPU registers etc. The leakage current of a transistor also leads to more power consumption. So there is a need to reduce the power consumption in each cell of a memory. In this paper, we focus on power optimization analysis of different SRAM cells using transistor stacking technique. Using this stacking technique, instead of using single size transistor, we use two half size transistors. Here we connect the transistors in series which are turned off. This reduces the leakage current which in turn reduces the power consumption of SRAM cell. In this paper power consumption is analyzed for various SRAM cells with and without stacking technique using at different voltages are simulated using Hspice-A 2008.03 tool.