Abstract
An approach is presented for power integrity analysis on multi-layer printed circuit boards in this paper. Two critical current paths are analyzed. Inductance decomposition is applied to identify the critical parameters that can influence the PDN input impedance. Two types of stack-ups are used to perform sensitivity analysis to illustrate the effectiveness of PDN design guidelines. Based on the analysis of the inductance contribution from different blocks in the PCB PDN, a systematic approach to obtain a complete understanding of PDN behavior is proposed. The approach can be used to provide design guidance in PDN design practice.
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