Power integrity modeling, measurement and analysis of seven-chip stack for TSV-based 3D IC integration

Abstract

This paper presents power integrity modeling, measurement and analysis of a seven-chip stack for through-silicon via (TSV)-based 3D IC integration. A hybrid full-wave and circuit approach, combined with a cascaded scattering matrix technique, is proposed to model the multi-chip stack consisting of TSVs, on-chip power grids and on-chip decoupling capacitors. The hybrid approach leverages the accuracy of a full-wave approach and shorter computational time of a circuit approach. Modeling results show good correlation with measurement from 1.1 GHz to 20.1 GHz. Power integrity analysis is then performed on the seven-chip stack. To the best of our knowledge, this is the first power integrity modeling, measurement and analysis of seven-chip stack including on-chip decoupling capacitors.