Abstract
In this paper, the new framework for power integrity analysis for core logic blocks is presented. Balancing on-chip timing budget becomes more challenging as both data and clock jitter increase due to large power noise. Conventional power integrity (PI) analysis focuses on reducing supply noise and does not provide timing jitter information. This paper proposes a general framework to model timing jitter due to supply noise. The proposed methodology can be used to define power distribution network (PDN) design requirements. This timing-based PDN design leads to significant reduction in the pessimism associated with either conventional target impedance concept, or static or dynamic power integrity analysis.
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