System-level design consideration and optimization of through-silicon-via inductor

Abstract

Due to the slow scaling of board and package technology, on-chip inductor has shown promising potential to enable more compact design and smaller parasitics for inductor-based designs, such as voltage regulator, resonant clocking, filter, etc. On the other hand, conventional on-chip 2D spiral inductor must be placed on the top metal layers, thereby consuming significant routing resources for global interconnects. Moreover, it may need more dedicated shielding to prevent unnecessary coupling, which further increases its occupied area. With the popularity of 2.5D and 3D chip architecture, Through-Silicon-Via (TSV) has been widely used, a significant portion of which are placed for thermal/manufacturability/reliability purposes. Thus, those redundant TSVs can be utilized to form the on-chip inductor for 2.5D/3D chips, with lower footprint and higher inductance density compared from the conventional spiral inductor. Unlike prior works focusing on the inductor itself, this paper discusses the optimization and application of such TSV-inductor from system perspective, including the optimization options and its design considerations. The possible design options including physical parameters, architecture and materials, to optimize the TSV-inductor are thoroughly investigated. Based on that, we further study a few key design scenarios to evaluate the design impact with use of such TSV-inductor and provide the design guidelines for its application in actual system designs.