Synthesis of low-power CMOS circuits using hybrid topologies

Abstract

This paper describes the development of a logic synthesis tool, BDDMAP, designed specifically to work with a reduced set cell library consisting of a combination of pass logic and standard CMOS topologies. Delay and statistical power models have been developed for pass logic cells to be used in our optimization algorithm. MCNC benchmarks were used to evaluate the tool and the proposed circuit topology against the results obtained from Synopsys’ Design Analyzer. An improvement of 34.5% in power-delay product was achieved when using our cell library and 42.3% when using a standard CMOS library.