Abstract

The article introduces a new high-level synthesis method for self-testable RTL designs. A basic feature of this method is a structural testability model which treats testability as a structural design style integrated in the design process. The main objective is to develop a system-level synthesis tool set mapping a behavioral description onto an optimized and testable RTL design subject to user-defined constraints. The approach involves several major components within the following system-level iteration: scheduling and allocation, constraint estimation, and testability tradeoffs. >

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