Synergy between 2.5/3D development and hybrid 3D Wafer Level Fanout

Abstract

Portable electronics have become ubiquitous tools for everyday living, with increasing semiconductor density required for the expanding functionality expected in each generation by consumers. This requires that the semiconductors in these devices have maximum feature densities in the smallest package volume, all with continually shrinking requirements for X, Y, and Z dimensions. In the past few years development has been ongoing for increasing the density achievable in the Z dimension. One such technology has been commonly called 2.5D, using a Silicon or Glass interposer, with through vias, between traditional Silicon die and the package substrate. The other option is the inclusion of Through Silicon Vias (TSVs) within the active dies themselves, allowing the stacking of these die directly onto the substrate. 2009 saw the first high volume production of Fan Out Wafer Level Fan Packaging (FOWLP) with the introduction of Infineon's eWLB products into the marketplace. These products have been in production with one IDM, and three Assembly subcontracting houses for several years now, primarily in the basic single die per package format. Development has been ongoing to expand the offering of FOWLP to include 2D multiple die and passives within the molded reconstituted fanout wafer, as well as multiple approaches for 3D double sided FOWLPs. FOWLP offers the possibility of manufacturing very thin Package on Package (POP) structures, as well as very thin 3D module assemblies. We have taken the technology developed internally for 2.5D and 3D packaging, and incorporated that learning to produce a hybrid 3D FOWLP package. The concept is to produce Silicon Interposer Die with TSVs that can be embedded along with the active die into a FOWLP to provide the required connectivity between the package front and back sides. The TSV die contains through vias that have the TSV conductor exposed for connectivity no matter what backgrind thickness of the package is desired. In addition to performing the function of front side to back side through connectivity, the front side of the TSV die can contain Redistribution traces (RDLs) across the length of the die. This allows crossover connectivity without the need for a second RDL layer on the Fanout package during processing, and can reduce final cost. The TSV die can also be processed to contain Integrated Passive Devices (IPDs) on the front surface of the die. The TSV and double sided processes which were developed at ASE for the generation of 2.5D Interposers and 3D Silicon die were adapted to the 3D processing of the Fanout Wafer Level Package. The process allows the Fanout package to be thinner than 0.5mm, and thus can achieve POP total package thicknesses of less than 1mm. This integration of technologies achieved a new Hybrid 3D package structure.