Cost trade-off analysis of PoP versus 3D TSV

Abstract

Smart phones and tablets continue to show strong growth. IDC predicts that smart phone shipments will grow from 472 million units in 2011 to 982 million by the end of 2015. Shipments of tablets will exceed 50 million units in 2012. These products make use of the 3D package-on-package (PoP) configuration where the top package typically contains memory and the bottom package contains logic such as a processor. Increasingly, the logic device in the bottom package is using flip chip, including copper pillar. Almost 600 million PoPs were shipped in 2011 [1] and the infrastructure for this package is well established. Performance requirements such as increased bandwidth and lower power are driving the adoption of 3D ICs designed with through silicon vias (TSVs). The timing for mass production in mobile applications depends on how the cost of the new technology compares with that of existing technologies. Designers must understand the total cost of each alternative including the effect of die yield versus package yield to choose the lowest cost options. For example, it is not enough to only calculate the processing cost and yield of TSVs when considering a 3D solution. Designers must also calculate the cost of using a known good die (KGD) or “pretty good” die (PGD) versus a packaged IC and the yield effect of that die on the cost of the total package. This paper provides an assessment of the total cost tradeoffs between PoP and 3D TSV. The cost and yield for PoP fabrication, PoP assembly, die yield, TSV, and die stacking are included. A break even analysis is also provided to highlight the 3D TSV required costs and yields to achieve the same cost as a PoP solution. An update of technology and business issues that are considered barriers to 3D TSV adoption is included.