Synchronous OEIC Integrating Receiver for ORGA Applications

Abstract

This work presents a monolithically integrated synchronous optical receiver fabricated in a standard 0.35μm CMOS process. The receiver consists of a regenerative latch acting as a sense amplifier; two highly effective, low-capacitance pin photodiodes connected to its output nodes (one of them blocked to the light); and an adjustable reference current to compensate the dynamic offset created by the asymmetries between the parasitic capacitances of the photodiodes. For λ = 635nm, a sensitivity of −25.8 dBm, −26.0 dBm, and −28.4dBm is obtained, respectively, for 400 Mbit/s, 350 Mbit/s, and 250 Mbit/s (BER = 10−9). The power consumption is 670μW, which translates to an energy efficiency of 1.7 pJ/bit at 400 Mbit/s.